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Engineering Specification
Engineering Specification Type 15.0 SXGA+ Color TFT/LCD Module Model Name:ITSX95 Document Control Number : OEM I-95-04
Note:Specification is subject to change without notice. Consequently it is better to contact to International Display Technology before proceeding with the design of your product incorporating this module.
Sales Support International Display Technology
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 1/29
Engineering Specification
i Contents
i Contents ii Record of Revision 1.0 Handling Precautions 2.0 General Description 2.1 Characteristics 2.2 Functional Block Diagram 3.0 Absolute Maximum Ratings 4.0 Optical Characteristics 5.0 Signal Interface 5.1 Connectors 5.2 Interface Signal Connector 5.3 Interface Signal Description 5.4 Interface Signal Electrical Characteristics 5.4.1 Signal Electrical Characteristics for LVDS Receiver 5.4.2 LVDS Receiver Internal Circuit 5.5 Signal for Lamp connector 6.0 Pixel format image 7.0 Parameter guide line for CFL Inverter 8.0 Interface Timings 8.1 Timing Characteristics 8.2 Timing Definition 9.0 Power Consumption 10.0 Power ON/OFF Sequence 11.0 Mechanical Characteristics 12.0 National Test Lab Requirement
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 2/29
Engineering Specification
ii Record of Revision
Date June 1,2000 Document Revision OEM95-01 Page All Summary First Edition for customer. Based on Internal Spec. as of March 10,2000. Based on Mechanical Drawing as of 24APR00. Based on Internal Specification EC F78951 as of July 12,2000. To update Characteristics. To add Note for Even/Odd. To update LVDS Macro AC characteristics. To update Timing Characteristics. To update Power Consumption. To update Power ON/OFF Sequence. To update Reference Drawing as of June 5,2000. Based on Internal Specification EC F78952 as of September 6,2000. To update Absolute Maximum Ratings (VDD). To update Optical Characteristics. To update Interface Signal Electrical Characteristics. To update Parameter guide line for CFL Inverter. To update Power Consumption. To update Reference Drawing as of September 1,2000. Based on Internal Specification EC H30700 as of January 31,2001. To avoid using "inch" indication. To update Weight. To update Reference Drawings. Updated by establishment of the New Company as "International Display Technology".
August 4,2000
OEM95-02 6 12 14 19 21 22 23,24
October 10,2000
OEM95-03 8 9 14,15,16,17,18 21 25 27,28
April 24,2001
OEM95-04 1,5,6,7 6 27,28
February 22,2002
OEM I-95-04
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 3/29
Engineering Specification
1.0 Handling Precautions
1) Since front polarizer is easily damaged, pay attention not to scratch it. 2) Be sure to turn off power supply when inserting or disconnecting from input connector. 3) Wipe off water drop immediately. Long contact with water may cause discoloration or spots. 4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth. 5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface. 6) Since CMOS LSI is used in this module, take care of static electricity and insure human earth when handling. 7) Do not open nor modify the Module Assembly. 8) Do not press the reflector sheet at the back of the module to any directions. 9) Do not stick the adhesive tape on the reflector sheet at the back of the LCD module. 10) In case if a Module has to be put back into the packing container slot after once it was taken out from the container, do not press the center of the CFL Reflector edge. Instead, press at the far ends of the CFL Reflector edge softly. Otherwise the TFT Module may be damaged. 11) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt the Interface Connector of the TFT Module. 12) After installation of the TFT Module into an enclosure ( Notebook PC Bezel, for example), do not twist nor bent the TFT Module even momentary. At designing the enclosure, it should be taken into consideration that no bending/twisting forces are applied to the TFT Module from outside. Otherwise the TFT Module may be damaged. 13) The fluorescent lamp in the liquid crystal display (LCD) contains mercury. Do not put it in trash that is disposed of in landfills. Dispose of it as required by local ordinances or regulations. 14)Small amount of materials having no flammability grade is used in the LCD module. The LCD module should be supplied by power complied with requirements of Limited Power Source (2.11, IEC60950 or UL1950), or be applied exemption conditions of flammability requirements (4.4.3.3, IEC60950 or UL1950) in an end product. 15)The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit (2.4, IEC60950 or UL1950). Do not connect the CFL in Hazardous Voltage Circuit.
O
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by International Display Technology for any infringements of patents or other right of the third partied which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of International Display Technology or others. The information contained herein may be changed without prior notice. It is therefore advisable to contact International Display Technology before proceeding with the design of equipment incorporationg this product.
O
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 4/29
Engineering Specification
2.0 General Description
This specification applies to the Type 15.0 Color TFT/LCD Module 'ITSX95'. This module is designed for a display unit of notebook style personal computer. The screen format and electrical interface are intended to support the SXGA+(1400(H) x 1050(V)) screen. Support color is native 262K colors(RGB 6-bit data driver). All input signals are LVDS(Low Voltage Differential Signaling) interface compatible. This module does not contain an inverter card for backlight.
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 5/29
Engineering Specification
2.1 Characteristics
The following items are characteristics summary on the table under 25 degree C condition: CHARACTERISTICS ITEMS Screen Diagonal [mm] Pixels H x V Active Area [mm] Pixel Pitch [mm] Pixel Arrangement Weight [grams] Physical Size [mm] Display Mode Support Color White Luminance [cd/m 2] Design Point 1:(ICFL=3.5mA) Design Point 2:(ICFL=6.5mA) Contrast Ratio Optical Rise Time/Fall Time [msec] Nominal Input Voltage VDD [Volt] Power Consumption [Watt](VDD Line) Lamp Power Consumption [Watt] (VCFL Line) Design Point 1:(ICFL=3.5mA) Design Point 2:(ICFL=6.5mA) Typical Power Consumption [Watt] (VDD Line + VCFL Line) Design Point 1:(ICFL=3.5mA) Design Point 2:(ICFL=6.5mA) Electrical Interface Temperature Range [degree C] Operating Storage (Shipping) SPECIFICATIONS 381 1400(x3) x 1050 304.5(H) x 228.375(V) 0.2175(per one triad) x 0.2175 R,G,B Vertical Stripe 590 Typ.,625 MAX. 317.3(W) x 242.0(H) x 6.0(D) typ./6.3(D) MAX. Normally White Native 262K colors(RGB 6-bit data driver) 90 Typ(center) 85 Typ(5 points average) 150 Typ(center)140 Typ(5 points average) 200 : 1 Typ. 30Typ.,50 Max. +3.3 Typ. 1.8 Typ.,3.2MAX.
2.6Typ.,(W/o inverter loss) 4.2Typ.,(W/o inverter loss)
4.5Typ.5.9MAX,(W/o inverter loss) 6.0Typ.7.7MAX,(W/o inverter loss) 8 pairs LVDS(Even/Odd R/G/B Data(6bit), 3sync signals, Clock) 0 to +50 -20 to +60
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 6/29
Engineering Specification
2.2 Functional Block Diagram
The following diagram shows the functional block of this Type 15.0 Color TFT/LCD Module. The first LVDS port transmits even pixels while the second LVDS port transmits odd pixels.
X-Driver Y-Driver < 8 pairs LVDS >
6bit color data for R/G/B (even/odd) DTCLK(even/odd) DSPTMG Vsync Hsync
EVEN PIXCEL ODD PIXCEL
LCD DRIVE CARD
Controller
Dual LVDS RECEIVER
LCD
TFT ARRAY/CELL 1400(R/G/B) x 1050
G/A
DC-DC Converter Ref circuit
Backlight Unit
VDD GND LCD-DRIVE Connector JAE FI-XB30S-HF10 (30pin) Lamp Connector JST BHSR-02VS-1 (2pin)
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 7/29
Engineering Specification
3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as follows : Item Logic/LCD Drive Voltage Input Signal Voltage CFL Ignition Voltage CFL Current CFL Peak Inrush Current Operating Temperature Operating Relative Humidity Storage Temperature Storage Relative Humidity Vibration Shock Symbol VDD VIN Vs ICFL ICFLP TOP HOP TST HST Min -0.3 -0.3 0 8 -20 5 Max +4.0 VDD+0.3 +1,600 +7 20 +50 95 +60 95 1.5 50 10-200 18 Unit V V Vrms mAms mA deg.C %RH deg.C %RH G G Hz ms Rectangle wave Note 1 Note 1 Note 1 Note 1 Note 2 Conditions
Note 1 : Maximum Wet-Bulb should be 39 degree C and No condensation. Note 2 : Duration : 50msec Max. Ta=0 degree C
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 8/29
Engineering Specification
4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25 degree C condition: Item Viewing Angle (Degrees) K:Contrast Ratio Contrast ratio Response Time (ms) Color Chromaticity (CIE) Rising Falling Red Red Green Green Blue Blue White White White Luminance (cd/m ) ICFL 6.5 mA
2
Conditions Horizontal K210 Vertical K210 (Right) (Left) (Upper) (Lower)
Specification Typ. 40 40 15 30 200 30 30 Note 50Max 50Max -
x y x y x y x y
0.569 0.332 0.312 0.544 0.149 0.132 0.313 0.329 150Typ. Center 140Typ. 5 points average
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 9/29
Engineering Specification
5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module. These connectors are capable of accommodating the following signals and will be following components. Connector Name / Designation Manufacturer Type / Part Number Mating Receptacle Manufacture Mating Receptacle/Part Number For Signal Connector JAE FI-XB30S-HF10 JAE FI-X30M
Connector Name / Designation Manufacturer Type / Part Number Mating Type / Part Number
For Lamp Connector JST BHSR-02VS-1 SM02B-BHSS-1
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 10/29
Engineering Specification
5.2 Interface Signal Connector
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Signal Name FG (GND) GND VDD VDD Reserved Reserved Reserved Reserved ReIN0ReIN0+ GND ReIN1ReIN1+ GND ReIN2ReIN2+ Pin # 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Signal Name GND ReCLKINReCLKIN+ GND RoIN0RoIN0+ GND RoIN1RoIN1+ GND RoIN2RoIN2+ GND RoCLKINRoCLKIN+ FG (GND)
Note: 'Reserved' pins are not allowed to connect any other line. Voltage levels of all input signals are LVDS compatible (except VDD). Refer to "Signal Electrical Characteristics for LVDS(*)", for voltage levels of all input signals.
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 11/29
Engineering Specification
5.3 Interface Signal Description
The module uses a pair of LVDS receiver SN75LVDS86(Texas Instruments) compatible. LVDS is a differential signal technology for LCD interface and high speed data transfer device. Transmitter shall be SN75LVDS84/85 or compatible. PIN # SIGNAL NAME Description
1 FG Frame Ground 2 GND Ground 3 VDD +3.3V Power Supply 4 VDD +3.3V Power Supply 5 Reserved Reserved 6 Reserved Reserved 7 Reserved Reserved 8 Reserved Reserved 9 ReIN0Negative LVDS differential data input (Even R0-R5, G0) 10 ReIN0+ Positive LVDS differential data input (Even R0-R5, G0) 11 GND Ground 12 ReIN1Negative LVDS differential data input (Even G1-G5, B0-B1) 13 ReIN1+ Positive LVDS differential data input (Even G1-G5, B0-B1) 14 GND Ground 15 ReIN2Negative LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG) 16 ReIN2+ Positive LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG) 17 GND Ground 18 ReCLKINNegative LVDS differential clock input (Even) 19 ReCLKIN+ Positive LVDS differential clock input (Even) 20 GND Ground 21 RoIN0Negative LVDS differential data input (Odd R0-R5, G0) 22 RoIN0+ Positive LVDS differential data input (Odd R0-R5, G0) 23 GND Ground 24 RoIN1Negative LVDS differential data input (Odd G1-G5, B0-B1) 25 RoIN1+ Positive LVDS differential data input (Odd G1-G5, B0-B1) 26 GND Ground 27 RoIN2Negative LVDS differential data input (Odd B2-B5) 28 RoIN2+ Positive LVDS differential data input (Odd B2-B5) 29 GND Ground 30 RoCLKINNegative LVDS differential clock input (Odd) 31 RoCLKIN+ Positive LVDS differential clock input (Odd) 32 FG Frame Ground Note: Input signals of odd and even clock shall be the same timing. The module uses a 100ohm resistor between positive and negative data lines of each receiver input. Even : First Pixel data Odd : Second Pixel Data
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 12/29
Engineering Specification
SIGNAL NAME +RED 5 +RED 4 +RED 3 +RED 2 +RED 1 +RED 0 (EVEN/ODD) +GREEN 5 +GREEN 4 +GREEN 3 +GREEN 2 +GREEN 1 +GREEN 0 (EVEN/ODD) +BLUE 5 +BLUE 4 +BLUE 3 +BLUE 2 +BLUE 1 +BLUE 0 (EVEN/ODD) -DTCLK (EVEN/ODD) +DSPTMG VSYNC HSYNC VDD GND
Description RED Data 5 (MSB) RED Data 4 RED Data 3 RED Data 2 RED Data 1 RED Data 0 (LSB) Red-pixel Data: Each red pixel's brightness data consists of these 6 bits pixel data. GREEN Data 5 (MSB) GREEN Data 4 GREEN Data 3 GREEN Data 2 GREEN Data 1 GREEN Data 0 (LSB) Green-pixel Data: Each green pixel's brightness data consists of these 6 bits pixel data. BLUE Data 5 (MSB) BLUE Data 4 BLUE Data 3 BLUE Data 2 BLUE Data 1 BLUE Data 0 (LSB) Blue-pixel Data: Each blue pixel's brightness data consists of these 6 bits pixel data. Data Clock: The typical frequency is 54MHz. The signal is used to strobe the pixel +data and the +DSPTMG Display Timing: When the signal is high, the pixel data shall be valid to be displayed. Vertical Sync: This signal is synchronized with -DTCLK. Both active high/low signals are acceptable. Horizontal Sync: This signal is synchronized with -DTCLK. Both active high/low signals are acceptable. +3.3V Power Supply Ground
Note: Output signals from any system shall be Hi-Z state when VDD is off.
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 13/29
Engineering Specification
5.4 Interface Signal Electrical Characteristics
5.4.1 Signal Electrical Characteristics for LVDS Receiver
Table . Electrical Characteristics Parameter Differential Input High Threshold Differential Input Low Threshold Magnitude Differential Input Voltage Common Mode Voltage Common Mode Voltage Offset Note: Symbol Vth Vtl |Vid| Vcm Vcm Min -100 100 0.825 +|Vid|/2 -50 Typ Max +100 600 2.4 -|Vid|/2 +50 Unit mV mV mV V mV Conditions
O Input signals shall be low or Hi-Z state when VDD is off.
Figure . Voltage Definitions
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 14/29
Engineering Specification
Table . Switching Characteristics Parameter Symbol Min Typ Max Unit Conditions Clock Frequency fc 51 54 57 MHz Cycle Time tc 17.5 18.5 19.6 ns Data Setup Time Tsu 700 ps fc = 54MHz, jitter < 50ps Data Hold Time Thd 700 ps Cycle modulation rate(Note) tCJavg 20 ps/clk Note: This specification defines maximum average cycle modulation rate in peak-to-peak transition within any 100 clock cycles. This specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps. Figure . Timing Definition (Even)
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 15/29
Engineering Specification
Figure . Timing Definition (Odd)
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 16/29
Engineering Specification
Figure . Timing Definition(detail A)
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 17/29
Engineering Specification
5.4.2 LVDS Receiver Internal Circuit
Below figure shows the internal block diagram of the LVDS receiver.
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 18/29
Engineering Specification
5.5 Signal for Lamp Connector
Pin # 1
2
Signal Name Lamp High Voltage Lamp Low Voltage
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 19/29
Engineering Specification
6.0 Pixel format image
Following figure shows the relationship of the input signals and LCD pixel format image. Even and odd pair of RGB data are sampled at a time.
Even 0 1st Line
R
Odd 1
R
Even 1398
R
Odd 1399
R
GB
GB
GB
GB
1050th Line
R
GB
R
GB
R
GB
R
GB
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 20/29
Engineering Specification
7.0 Parameter guide line for CFL Inverter
PARAMETER White Luminance (Center) (5 Points average) CFL current(ICFL) CFL Frequency(FCFL) CFL Ignition Voltage(Vs) MIN DP-1 DP-2 MAX UNITS cd/m2 3.0 40 1,500 90 85 3.5 150 140 6.5 7.0 60 mArms KHz Vrms (Ta=25 deg.C) (Ta=25 deg.C) Note 1 (Ta= 0 deg.C) Note 3 (Ta=25 deg.C) Note 2 (Ta=25 deg.C) Note 2 CONDITION (Ta=25 deg.C)
CFL Voltage (Reference)(VCFL) CFL Power consumption(PCFL)
-
730 2.6
635 4.2
-
Vrms W
Note 1: CFL discharge frequency should be carefully determined to avoid interference between inverter and TFT LCD. Note 2: Calculated value for reference (ICFL x VCFL = PCFL). Note 3: CFL inverter should be able to give out a power that has a generating capacity of over 1,500 voltage. Lamp units need 1,500 voltage minimum for ignition. Note 4: DP-1 and DP-2 are recommended Design Points. *1 All of characteristics listed are measured under the condition using the Test inverter. *2 In case of using an inverter other than listed, it is recommended to check the inverter carefully. Sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen. *3 In designing an inverter, it is suggested to check safety circuit very carefully. Impedance of CFL, for instance, becomes more than 1 [M ohm] when CFL is damaged. *4 Generally, CFL has some amount of delay time after applying kick-off voltage. It is recommended to keep on applying kick-off voltage for 1 [Sec] until discharge. *5 CFL discharge frequency must be carefully chosen so as not to produce interfering noise stripes on the screen. *6 Reducing CFL current increases CFL discharge voltage and generally increases CFL discharge frequency. So all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high-voltage output of the inverter. *7 It should be employed the inverter which has 'Duty Dimming', if ICFL is less than 4[mA].
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 21/29
Engineering Specification
The following chart is CFL current versus the luminance for your reference.
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 22/29
Engineering Specification
8.0 Interface Timings
Basically, interface timings described here is not actual input timing of LCD module but output timing of SN75LVDS86(Texas Instruments) or equivalent.
8.1 Timing Characteristics
Signal DTCLK Item Freqency Symbol Fdck Tck +V-Sync Frame Rate Fv Tv Nv V-Active Level Tva Nva V-Back Porch V-Front Porch +DSPTMG +H-Sync V-Line Scan Rate Nvb Nvf m Fh Th Nh H-Active Level Tha Tha H-Back Porch H-Front Porch +DSPTMG +DATA Display Data Even/Odd Thb Thf Thd n 8 26 8 762 1058 15.78 1 6 1 MIN. 51 TYP. 54 18.5 60 16.67 1066 46.7 3 12 1 1050 63.98 15.63 844 1.037 56 64 24 12.96 1400 250 300 1023 62 125 2046 MAX. 57 Unit [MHz] [ns] [Hz] [ms] [lines] [us] [lines] [lines] [lines] [lines] [KHz] [usec] [Tck] [usec] [Tck] [Tck] [Tck] [usec] [dots]
Note:Both positive Hsync and positive Vsync polarity is recommended
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 23/29
Engineering Specification
8.2 Timing Definition
Vertical Timing Support mode Tvblk Vertical Blanking 0.250 ms (16 lines) m Active Field 16.411 ms (1050 lines) Tvf VSYNC Front Porch 0.016 ms (1 line) Tv,Nv Frame Time 16.661 ms (1066 lines) Tva VSYNC Width 0.047 ms (3 lines) Tvb VSYNC Back Porch 0.188 ms (12 lines)
1400 x 1050 at 60Hz (H line rate : 15.63 us)
DSPTMG
Tv Tvf Tvblk Tva m Tvb
-VSYNC +VSYNC
Horizontal Timing Support mode 1400 x 1050 Dotclock : 108.000 MHz (54.000MHz x2) Thblk Horizontal Blanking 2.667 us (288 dots) Thd Active Field 12.963 us (1400 dots) Thf HSYNC Front Porch 0.444 us (48 dots) Th,Nh H Line Time 15.630 us (1688 dots) Tha HSYNC Width 1.037 us (112 dots) Thb HSYNC Back Porch 1.185 us (128 dots)
DSPTMG
Th Thf Thblk Tha Thd Thb
-HSYNC +HSYNC
Tck
VIDEO(Even) VIDEO(Odd) DTCLK
0 1
2 3
4 5
n-4 n-3
n-2 n-1
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 24/29
Engineering Specification
9.0 Power Consumption
Input power specifications are as follows; SYMBOL VDD PDD PDD PARAMETER Logic/LCD Drive Voltage VDD Power Max VDD Power 1.8 Min 3 Typ 3.3 Max 3.6 3.2 UNITS V W W CONDITION Load Capacitance 40uF MAX Pattern VDD=3.6V All Black Pattern VDD=3.3V MAX Pattern VDD=3.6V All Black Pattern VDD=3.3V
IDD Max IDD VDDrp
IDD Current Max IDD Current Allowable Logic/LCD Drive Ripple Voltage Allowable Logic/LCD Drive Ripple Noise 545
890
mA mA
100
mVp-p
VDDns
100
mVp-p
Note:Max Pattern:2 dot Vertical sub-pixel stripe.
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 25/29
Engineering Specification
10.0 Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from any system shall be Hi-Z state or low level when VDD is off.
150ms min.
VDD
0V
90% 10%
90% 10% 10%
10ms max. 0 min.
90% 90% 10%
0 min.
Signals
0V
10%
100ms min. 180ms min. (Recommended).
20ms min.
Lamp
On
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 26/29
Engineering Specification
11.0 Mechanical Characteristics
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 27/29
Engineering Specification
(C) Copyright International Display Technology 2002 All Rights reserved. February 22,2002 OEM I-95-04 28/29
Engineering Specification
12.0 National Test Lab Requirement
The display module is authorized to Apply the UL Recognized Mark.
Conditions of Acceptability
O
O O O O O
This component has been judged on the basis of the required spacings in the Standard for Safety of Information Technology Equipment, Including Electrical Business Equipment, CAN/CSA C22.2 No.950-95 *UL 1950, Third Edition, including revisions through revision date March 1,1998, which are based on the Fourth Amendment to IEC 950, Second Edition, which would cover the component itself if submitted for Listing. CF Lamp circuit for this model should be supplied from Limited Current Circuit. The units are supplied by Limited Power Sources. The terminals and connectors are suitable for factory wiring only. The terminals and connectors have not been evaluated for field wiring. A suitable Electrical and Fire enclosure shall be provided.
****** End Of Page ******
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